产品概述
描述
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture technology.
The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.
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所有功能
- Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)
- Compliant with Power Architecture®embedded category
- Variable Length Encoding (VLE)
- Memory organization
- Up to 256 KB on-chip code flash memory with ECC and erase/program controller
- Additional 64 (4 × 16) KB on-chip data flash memory with ECC for EEPROM emulation
- Up to 20 KB on-chip SRAM with ECC
- Fail-safe protection
- Programmable watchdog timer
- Non-maskable interrupt
- Fault collection unit
- Nexus Class 1 interface
- Interrupts and events
- 16-channel eDMA controller
- 16 priority level controller
- Up to 25 external interrupts
- PIT implements four 32-bit timers
- 120 interrupts are routed via INTC
- 1 general purpose eTimer unit
- 6 timers each with up/down capabilities
- 16-bit resolution, cascadable counters
- Quadrature decode with rotation direction flag
- Double buffer input capture and output compare
- GPIO (37 on LQFP64; 64 on LQFP100) individually programmable as I/O or special function
- Communications interfaces
- 2 LINFlex channels (1× Master/Slave, 1× Master only)
- Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip selects)
- Up to 2 FlexCAN interface (2.0B Active) with 32 message buffers
- 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at 64 MHz capability usable as second CAN when not used as safety port
- One 10-bit analog-to-digital converter (ADC)
- Up to 16 input channels (16 on LQFP100 / 12 on LQFP64)
- Conversion time < 1 μs including sampling time at full precision
- Programmable Cross Triggering Unit (CTU)
- 4 analog watchdogs with interrupt capability
- On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
- 1 FlexPWM unit: 8 complementary or independent outputs with ADC synchronization signals
- Up to 64 MHz, single issue, 32-bit CPU core complex (e200z0h)
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符号
封装
3D模型
质量与可靠性
| 产品型号 | Marketing Status | 包 | 等级规格 | 符合RoHS级别 | 材料声明** |
|---|---|---|---|---|---|
| SPC560P40L1CEFAR | 批量生产 | LQFP 64 10x10x1.4 mm | 汽车应用 | Ecopack2 | |
| SPC560P40L1CEFBR | 批量生产 | LQFP 64 10x10x1.4 mm | 汽车应用 | Ecopack2 |
(**) st.com上提供的材料声明表单可能是基于包装系列中最常用的封装的通用文档。因此，它们可能不是100%适用于特定的设备。有关特定设备的信息，请联系 销售支持。
样片和购买
| 产品型号 | 供货状态 | Budgetary Price (US$)*/Qty | 从ST订购 | Order from distributors | 包 | 包装类型 | RoHS | Country of Origin | ECCN (US) | ECCN (EU) | Operating temperature (°C) | Operating Temperature (°C) (max) | CPU Clock Frequency (MHz) (max) | Features set | Flash Size (kB) (Data) | ||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 最小值 | 最大值 | ||||||||||||||||
| SPC560P40L1CEFAR | | | distributors 无法联系到经销商，请联系我们的销售办事处 |
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| SPC560P40L1CEFBR | | | distributors 无法联系到经销商，请联系我们的销售办事处 |
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SPC560P40L1CEFAR 批量生产
SPC560P40L1CEFBR 批量生产